An analog-to-digital converter (ADC) converts an applied analog input signal into a digital output signal. ADCs find application in a wide variety of communication, storage and signal processing applications. Examples of different types of ADCs known to those skilled in the art include successive approximation register (SAR) ADCs, as well as other types of ADCs in which conversion is performed in multiple stages, such as pipelined ADCs and sub-ranging ADCs.
It is also known to implement a time-interleaved ADC as a combination of multiple ADCs operating in parallel, each of which may comprise a SAR ADC or other type of ADC. In one example of such an arrangement, m parallel n-bit ADCs each operate at a fractional sampling rate of fs/m, where fs is the overall sampling rate of the time-interleaved ADC. The time-interleaved ADC produces an n-bit output at the sampling rate fs by interleaving the outputs of the m individual ADCs. The time-interleaved ADC generally includes an input track-and-hold circuit. The input track-and-hold circuit may be implemented using an amplifier, also commonly referred to as a sample-and-hold amplifier (SHA), which operates at the sampling rate fs and drives each of the m individual ADCs.
The SHA may be configured as a flip-around SHA with bottom-plate sampling, as described in, for example, C. Hsu et al., “A CMOS 33-mW 100-MHz 80-dB SFDR Sample-and-Hold Amplifier,” IEICE Transactions on Electronics, Vol. E86-C, No. 10, pp. 2122-2128, October 2003, and R. Trivedi, “Low Power and High Speed Sample-and-Hold Circuit,” 49th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS '06), Aug. 6-9, 2006, pp. 453-456. Other examples of conventional SHAs are disclosed in U.S. Patent Application Publication No. 20120068766, entitled “Sample-and-Hold Amplifier.
The above-noted SHAs and other types of conventional track-and-hold circuits can be difficult to implement in practice due to the limited headroom provided for analog circuitry by modern CMOS processes. Also, with the short channel transistors generally used to meet high-speed requirements, it can be difficult to obtain sufficient gain within the track-and-hold circuit. This is particularly true for track-and-hold circuits in time-interleaved ADCs such as those that may be utilized in implementation of high-speed Serializer-Deserializer (SerDes) links in communication applications.